PACVGA105_11 Datasheet, PDF (2/6 Pages) ON Semiconductor – VGA Port Companion Circuit

R
G
B
GNDA
V_RGB
PACVGA105
SIMPLIFIED ELECTRICAL SCHEMATIC
V_CC
V_AUX
1.8 kW
DDC_CLK
1.8 kW
50 kW
50 kW
DDC_DATA
HSYNC
VSYNC
GNDD
VSYNC_OUT
HSYNC_OUT
PACKAGE / PINOUT DIAGRAMS
HSYNC_OUT
HSYNC
GNDD
V_RGB
B
G
R
GNDA
Top View
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
16−Pin QSOP
V_CC
VSYNC_OUT
VSYNC
V_AUX
DDC_CLK
GNDD
DDC_DATA
V_CC
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1
HSYNC_OUT Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line.
2
HSYNC
Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line.
3, 11
GNDD
Digital ground reference supply pin.
4
V_RGB
V_RGB supply pin. This is an isolated supply pin for the R, G and B ESD protection circuits.
5
B
Blue signal video protection channel. This pin is typically tied to the B video line between the VGA
controller device and the video connector.
6
G
Green signal video protection channel. This pin is typically tied to the G video line between the VGA
controller device and the video connector.
7
R
Red signal video protection channel. This pin is typically tied to the R video line between the VGA
controller device and the video connector.
8
GNDA
Analog ground reference supply pin.
9, 16
V_CC
V_CC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and
ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes
present on the HSYNC_OUT and VSYNC_OUT lines.
10
DDC_DATA DDC data pin.
12
DDC_CLK DDC clock pin.
13
V_AUX
V_AUX supply pin. This is the supply input for the 50 kW pullups connected to the HSYNC and VSYNC
buffer inputs.
14
VSYNC
Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line.
15
VSYNC_OUT Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line.
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