NPN2N3773 Datasheet, PDF (4/6 Pages) ON Semiconductor – Complementary Silicon Power Transistors

NPN 2N3773*, PNP 2N6609
30
20
10
5.0
3.0
2.0
1.0
0.5
0.3
0.2
0.1
0.05
0.03
3.0
10 ms
40 ms
100 ms
dc
200 ms
1.0 ms
100 ms
BONDING WIRE LIMIT
THERMAL LIMIT
@ T_C = 25°C, SINGLE PULSE
SECOND BREAKDOWN LIMIT
500 ms
5.0 7.0 10 20 30 50 70 100 200 300
V_CE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 7. Forward Bias Safe Operating Area
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I_C − V_CE
limits of the transistor that must be observed for reliable
operation: i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 7 is based on T_J(pk) = 200_C; T_C is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T_J(pk)
< 200_C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
100
80
60
40
20
0
0
THERMAL
DERATING
40
80
120
160
200
T_C, CASE TEMPERATURE (°C)
Figure 8. Power Derating
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