MTV16N50E Datasheet, PDF (4/10 Pages) Motorola, Inc – TMOS POWER FET 16 AMPERES 500 VOLTS RDS(on) = 0.40 OHM

MTV16N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
The capacitance (C_iss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t_d(on) and is read at a voltage corresponding to
the on−state when calculating t_d(off).
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for
complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance
source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate
which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate
produces a voltage at the source which reduces the gate
of average input current (I_G(AV)) can be made from a
rudimentary analysis of the drive circuit so that
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
t = Q/I_G(AV)
During the rise and fall time interval when switching a
resistive load, V_GS remains virtually constant at a level
known as the plateau voltage, V_SGP. Therefore, rise and fall
times may be approximated by the following:
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
t_r = Q₂ x R_G/(V_GG − V_GSP)
t_f = Q₂ x R_G/V_GSP
where
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
V_GG = the gate drive voltage, which varies from zero to V_GG
R_G = the gate drive resistance
and Q₂ and V_GSP are read from the gate charge curve.
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
During the turn−on and turn−off delay times, gate current is
inductive; the data in the figure is taken with a resistive load,
not constant. The simplest calculation uses appropriate
which approximates an optimally snubbed inductive load.
values from the capacitance curves in a standard equation
Power MOSFETs may be safely operated into an inductive
for voltage change in an RC network. The equations are:
load; however, snubbing reduces switching losses.
t_d(on) = R_G C_iss In [V_GG/(V_GG − V_GSP)]
t_d(off) = R_G C_iss In (V_GG/V_GSP)
7000
V_DS = 0 V
6000 ^Ciss
V_GS = 0 V
T_J = 25°C
5000
4000 _Crss
C_iss
3000
2000
1000
C_oss
0
−10 −5
C_rss
0
5
10
15
20
25
V_GS
V_DS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7a. Low Voltage Capacitance Variation
10000
1000
V_GS = 0 V
T_J = 25°C
C_iss
C_oss
100
C_rss
10
0
10
100
10
V_DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance Variation
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