MMDF5N02Z Datasheet, PDF (4/12 Pages) Motorola, Inc – DUAL TMOS POWER MOSFET 5.0 AMPERES 20 VOLTS

MMDF5N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge con-
trolled. The lengths of various switching intervals (∆t) are
determined by how fast the FET input capacitance can be
charged by current from the generator.
The published capacitance data is difficult to use for calcu-
lating rise and fall because drain−gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data
is used. In most cases, a satisfactory estimate of average in-
put current (I_G(AV)) can be made from a rudimentary analy-
sis of the drive circuit so that
t = Q/I_G(AV)
During the rise and fall time interval when switching a resis-
tive load, V_GS remains virtually constant at a level known as
the plateau voltage, V_SGP. Therefore, rise and fall times may
be approximated by the following:
t_r = Q₂ x R_G/(V_GG − V_GSP)
t_f = Q₂ x R_G/V_GSP
where
V_GG = the gate drive voltage, which varies from zero to V_GG
R_G = the gate drive resistance
and Q₂ and V_GSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t_d(on) = R_G C_iss In [V_GG/(V_GG − V_GSP)]
t_d(off) = R_G C_iss In (V_GG/V_GSP)
The capacitance (C_iss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when cal-
culating t_d(on) and is read at a voltage corresponding to the
on−state when calculating t_d(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance
is affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure
is taken with a resistive load, which approximates an opti-
mally snubbed inductive load. Power MOSFETs may be
safely operated into an inductive load; however, snubbing
reduces switching losses.
1400
V_DS = 0 V
1200
V_GS = 0 V
T_J = 25°C
1000 _Ciss
800
600 ^Crss
C_iss
400
C_oss
200
C_rss
0−10
−5
0
5
10
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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