MC84-74HC393 Datasheet, PDF (4/7 Pages) ON Semiconductor – Dual 4-Stage Binary Ripple Counter

MC54/74HC393
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flip–flops are toggled and the
counter state advances on high–to–low transitions of the
clock input.
CONTROL INPUTS
Reset (Pins 2, 12)
Active–high, asynchronous reset. A separate reset is pro-
vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
CLOCK
Q
tf
tr
90%
50%
10%
90%
50%
10%
tw
1/fmax
tPLH
tPHL
tTLH
tTHL
Figure 1.
SWITCHING WAVEFORMS
VCC
tw
RESET
50%
VCC
GND
GND
tPHL
Q
CLOCK
50%
trec
VCC
50%
GND
Figure 2.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 3. Test Circuit
EXPANDED LOGIC DIAGRAM
CLOCK ^{1, 13}
CQ
DQ
3, 11 _Q1
CQ
DQ
4, 10 _Q2
CQ
DQ
5, 9 _Q3
CQ
DQ
6, 8 _Q4
RESET ^{2, 12}
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6