MC84-74HC393 Datasheet, PDF (1/7 Pages) ON Semiconductor – Dual 4-Stage Binary Ripple Counter

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Stage
Binary Ripple Counter
High–Performance Silicon–Gate CMOS
The MC54/74HC393 is identical in pinout to the LS393. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.
Internal flip–flops are triggered by high–to–low transitions of the clock
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates
LOGIC DIAGRAM
CLOCK ^{1, 13}
BINARY
COUNTER
RESET ^{2, 12}
PIN 14 = VCC
PIN 7 = GND
3, 11 _Q1
4, 10 _Q2
5, 9 _Q3
6, 8 _Q4
MC54/74HC393
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
CLOCK a 1
RESET a 2
Q1a 3
Q2a 4
Q3a ₅
Q4a 6
GND 7
14 VCC
13 CLOCK b
12 RESET b
11 Q1b
10 Q2b
9 Q3b
8 Q4b
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
X
H
L
H
L
No Change
L
L
No Change
L
No Change
L
Advance to
Next State
10/95
© Motorola, Inc. 1995
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