MC74VHCT32A_11 Datasheet, PDF (4/7 Pages) ON Semiconductor – Quad 2-Input OR Gate / CMOS Logic Level Shifter

MC74VHCT32A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{TA = 25°C}
T_A = − 40 to 125°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, V_CC = 3.3 ± 0.3 V C_L = 15 pF
A or B to Y
C_L = 50 pF
5.5
7.9
1.0
9.5
ns
8.0
11.4
1.0
13.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC=5.0±0.5V CL=15pF
C_L = 50 pF
3.8
5.5
1.0
6.5
5.3
7.5
1.0
8.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Maximum Input Capacitance
4
10
10
pF
Typical @ 25°C, V_CC = 5.0V
C_PD
Power Dissipation Capacitance (Note 1)
22
pF
1. C_PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I_CC(OPR) = C_PD  V_CC  f_in + I_CC / 4 (per gate). C_PD is used to determine the
no−load dynamic power consumption; P_D = C_PD  V_CC2  f_in + I_CC  V_CC.
A
t_PLH
Y
1.5V
1.5V
3V
GND
t_PHL
V_OH
V_OL
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
ORDERING INFORMATION
Device
Package
Shipping^†
MC74VHCT32ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT32ADTR2G
TSSOP−14*
2500 / Tape & Reel
MC74VHCT32AMG
SOEIAJ−14
(Pb−Free)
50 Units / Rail
MC74VHCT32AMELG
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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