MC74VHCT32A_11 Datasheet, PDF (2/7 Pages) ON Semiconductor – Quad 2-Input OR Gate / CMOS Logic Level Shifter

MC74VHCT32A
V_CC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
1234567
A1 B1 Y1 A2 B2 Y2 GND
1
A1
B1 ²
4
A2
5
B2
9
A3
10
B3
12
A4
13
B4
3
Y1
6
Y2
Y = A)B
8
Y3
11 _Y4
Figure 1. Pin Connection and Marking Diagram (Top View)
Figure 2. Logic Diagram
Table 1. FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
H
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _VCC
DC Supply Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Vin
DC Input Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Vout
DC Output Voltage
V_CC = 0
High or Low State
–0.5 to +7.0
V
–0.5 to +7.0
V
–0.5 to +7.0
V
–0.5 to V_CC + 0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _IIK
Input Diode Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _IOK
Output Diode Current (V_OUT < GND; V_OUT > V_CC)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iout
DC Output Current, per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ICC
DC Supply Current, V_CC and GND Pins
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _PD
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
−20
mA
±20
mA
±25
mA
±50
mA
500
mW
450
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Tstg
Storage Temperature
–65 to +150
°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the}
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance
circuit. For proper operation, V_in and V_out should be constrained to the range GND v (V_in or V_out) v V_CC. Unused inputs must
always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused outputs must be left open.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
http://onsemi.com
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