MC74LVX125_11 Datasheet, PDF (4/7 Pages) ON Semiconductor – Quad Bus Buffer

MC74LVX125
NOISE CHARACTERISTICS (Input t_r = t_f = 3.0ns, C_L = 50pF, V_CC = 3.3V, Measured in SOIC Package)
T_A = 25°C
Symbol
Characteristic
Typ
Max
Unit
V_OLP Quiet Output Maximum Dynamic V_OL
0.3
0.5
V
V_OLV Quiet Output Minimum Dynamic V_OL
−0.3
−0.5
V
V_IHD Minimum High Level Dynamic Input Voltage
2.0
V
V_ILD Maximum Low Level Dynamic Input Voltage
0.8
V
ORDERING INFORMATION
Device
Package
Shipping^†
MC74LVX125DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74LVX125DR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
MC74LVX125DTG
TSSOP−14*
96 Units / Rail
MC74LVX125DTR2G
TSSOP−14*
2500 Tape & Reel
MC74LVX125MG
SOEIAJ−14
2000 Tape & Reel
MC74LVX125MELG
SOEIAJ−14
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
SWITCHING WAVEFORMS
D
50%
t_PLH
O
50% V_CC
V_CC
OE
GND
t_PHL
O
O
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
TEST CIRCUITS
DEVICE
UNDER
TEST
50%
t_PZL
t_PLZ
50% V_CC
t_PZH
t_PHZ
50% V_CC
Figure 4.
V_CC
GND
HIGH
IMPEDANCE
V_OL +0.3V
V_OH -0.3V
HIGH
IMPEDANCE
TEST POINT
OUTPUT
1 kW
C_L*
CONNECT TO V_CC WHEN
TESTING t_PLZ AND t_PZL.
CONNECT TO GND WHEN
TESTING t_PHZ AND t_PZH.
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
*Includes all probe and jig capacitance
Figure 6. Three−State Test Circuit
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