MC74HCT574A_05 Datasheet, PDF (4/7 Pages) ON Semiconductor – Octal 3−State Noninverting D Flip−Flop with LSTTL−Compatible Inputs

MC74HCT574A
AC ELECTRICAL CHARACTERISTICS (V_CC = 5.0 V ± 10%, C_L = 50 pF, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
– 55 to
25_C
v 85_C v 125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{fMAX Maximum Clock Frequency (50% Duty Cycle) (Figures 3 and 6)}
30
24
20
MHz
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
30
38
45
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
28
35
42
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPZH,
t_PZL
Maximum Propagation Delay Time, Output Enable to Q
(Figures 4 and 7)
28
35
42
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTHL
Maximum Output Transition Time, Any Output
(Figures 3, 4 and 6)
12
15
18
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Cin Maximum Input Capacitance}
10
10
10
pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON}
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Flip−Flop)*
58
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (V_CC = 5.0 V ± 10%, C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55 to 25_C
v 85_C
v 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tsu
t_h
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tr, If}
Parameter
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
Minimum Pulse Width, Clock
Maximum Input Rise and Fall Times
Figure
5
5
3
3
Min
Max
Min
Max
Min
10
13
15
5.0
5.0
5.0
15
19
22
500
500
Max _Unit
ns
ns
ns
500
ns
CLOCK ¹¹
ENABLE 1
OUTPUT
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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