MC74HCT373A_06 Datasheet, PDF (4/8 Pages) ON Semiconductor – Octal 3−State Noninverting Transparent Latch with LSTTL−Compatible Inputs

MC74HCT373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _DICC
Additional Quiescent Supply V_in = 2.4 V, Any One Input
5.5
Current
V_in = V_CC or GND, Other Inputs
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{lout = 0 mA}
≥ −55°C
2.9
25°C to 125°C mA
2.4
NOTE: 1. Total Supply Current = I_CC + SDI_CC.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (V_CC = 5.0 V ± 10%, C_L = 50 pF, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
– 55 to
25°C
v 85°C v 125°C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
35
42
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
32
40
48
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLZ,
t_PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
30
38
45
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPZL,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
35
44
53
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Cin
Maximum Input Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Cout
Maximum Three−State Output Capacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Output in High−Impedance State)}
10
10
10
pF
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD
Power Dissipation Capacitance (Per Latch)*
65
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (V_CC = 5.0 V ± 10%, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tsu
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^th
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_r, t_f
Parameter
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch Enable
(Figure 2)
Maximum Input Rise and Fall Times
(Figure 1)
Guaranteed Limit
– 55 to
25°C
v 85°C v 125°C Unit
10
13
15
ns
10
13
15
ns
12
15
18
ns
500
500
500
ns
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