MC74HC574A_14 Datasheet, PDF (4/9 Pages) ON Semiconductor – Octal 3-State Noninverting D Flip-Flop

MC74HC574A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF; Input t_r = t_f = 6.0 ns)
V_CC
V
Symbol
Parameter
f_max Maximum Clock Frequency (50% Duty Cycle)
2.0
(Figures 2 and 5)
3.0
4.5
6.0
t_PLH, Maximum Propagation Delay, Clock to Q
2.0
t_PHL (Figures 2 and 5)
3.0
4.5
6.0
t_PLZ, Maximum Propagation Delay, Output Enable to Q
2.0
t_PHZ (Figures 3 and 6)
3.0
4.5
6.0
t_PZL, Maximum Propagation Delay, Output Enable to Q
2.0
t_PZH (Figures 3 and 6)
3.0
4.5
60
t_TLH, Maximum Output Transition Time, any Output
2.0
t_THL (Figures 2 and 5)
3.0
4.5
6.0
C_in Maximum Input Capacitance
C_out Maximum Three−State Output Capacitance, Output in High−Impedance
State
Guaranteed Limit
−55 to 25_C ≤ 85_C ≤ 125_C
6.0
4.8
4.0
15
10
8.0
30
24
20
35
28
24
160
200
240
105
145
190
32
40
48
27
34
41
150
190
225
100
125
150
30
38
45
26
33
38
140
175
210
90
120
140
28
35
42
24
30
36
60
75
90
27
32
36
12
15
18
10
13
15
10
10
10
15
15
15
Unit
MHz
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Enabled Output)*
24
pF
*Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
TIMING REQUIREMENTS (C_L = 50 pF; Input t_r = t_f = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
V_CC –55 to 25_C
≤ 85_C
≤ 125_C
Figure Volts Min Max Min Max Min Max Unit
t_su
Minimum Setup Time, Data to Clock
4
2.0 50
65
75
ns
3.0 40
50
60
4.6 10
13
15
6.0 9.0
11
13
t_h
Minimum Hold Time, Clock to Data
4
2.0 5.0
5.0
5.0
ns
3.0 5.0
5.0
5.0
4.5 5.0
5.0
5.0
6.0 5.0
5.0
5.0
t_w
Minimum Pulse Width, Clock
2
2.0 75
3.0 60
4.5 15
6.0 13
95
110
ns
80
90
19
22
16
19
t_r, t_f
Maximum Input Rise and Fall Times
2
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000 ns
800
500
400
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