MC33565 Datasheet, PDF (4/8 Pages) ON Semiconductor – 200 mA INTELLIGENT LDO REGULATOR WITH SMART BYPASS CONTROL

+3.3 Vin
MC33565
Compensation
&
Hysteresis
Hyst sw
Comp
Driver _{Drive out}
Ref &
Detect _Vref
5V detect
External
P–channel
MOSFET
+3.3 Vout
+5 Vin
+3.3 Vout
Sense in
External
LDO
4.7 µF
cap
Figure 1. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Input Blocking – The internal NPN pass transistor of the
LDO regulator ensures that no significant reverse current will
flow from +3.3 Vout back to the +5 Vin input when the 5V input
is not powered and the 3.3 Vin supply is present.
5 Volt Detect – Internal circuitry detects the presence of
the 5V input supply. When the 5V supply drops below a given
threshold, the +3.3 Vin bypass transistor (an external
P–channel MOSFET) is enabled. The 5V detect logic is
active throughout the entire range of ramp–up from 0 to 5.5V.
Additionally, the Drive out signal is never turned ON or OFF
inappropriately during ramp–up of the +5 Vin supply. Also,
+3.3 Vout never drops below 3.0V while +5 Vin is above the
5V detect minimum threshold.
Glitch–free Transfer – The design of the 5V detect
circuitry and Drive out control circuitry guarantees that the
+3.3 Vout will not exceed the output voltage specification
listed in the table of DC Operating Specifications even with
+5 Vin ramping up and down at the extremes of the slew rates
in the table of AC Operating Specifications (provided the
device is used with an MGSF1P02ELT PMOS FET on Drive
out along with a minimum 4.7µF capacitor on the +3.3 Vout).
Offset Voltage Performance – To ensure performance
when external offsets are present on the +5 Vin and +3.3 Vin
power inputs, the device has been designed to be capable of
operating with either one or both of these inputs rising from or
falling to zero volts, or with offsets of 0.05V to 0.9V as the
inputs ramp up and down.
3.3V aux
Motherboard/
Mainboard
5V
PCI Slot
+5 Vin
1
N/C
2
+3.3 Vin
3
Gnd
4
Drive out
8
+3.3 Vout
7
MC33565
Sense in
6
N/C
5
PCI NIC/Card
Circuitry
4.7 µF
Figure 2. Application Block Diagram
4
MOTOROLA ANALOG IC DEVICE DATA