MC14517B Datasheet, PDF (4/8 Pages) ON Semiconductor – Dual 64-Bit Static Shift Register

MC14517B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS ^(6.) (C_L = 50 pF, T_A = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
V_DD
Min
Typ ^(7.)
Max
Unit
Output Rise and Fall Time
t_TLH, t_THL = (1.5 ns/pF) C_L + 25 ns
t_TLH, t_THL = (0.75 ns/pF) C_L + 12.5 ns
t_TLH, t_THL = (0.65 ns/pF) C_L + 9.5 ns
t_TLH, t_THL
ns
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
t_PLH, t_PHL = (1.7 ns/pF) C_L + 390 ns
t_PLH, t_PHL = (0.66 ns/pF) C_L + 177 ns
t_PLH, t_PHL = (0.5 ns/pF) C_L + 115 ns
t_PLH, t_PHL
ns
5.0
—
475
770
10
—
210
300
15
—
140
215
Clock Pulse Width
t_WH
5.0
330
170
—
ns
10
125
75
—
15
100
60
—
Clock Pulse Frequency
f_cl
5.0
—
3.0
1.5
MHz
10
—
6.7
4.0
15
—
8.3
5.3
Clock Pulse Rise and Fall Time
t_TLH, t_THL
5.0
10
15
—
See Note ^(8.)
Data to Clock Setup Time
t_su
5.0
0
– 40
—
ns
10
10
– 15
—
15
15
0
—
Data to Clock Hold Time
t_h
5.0
150
75
—
ns
10
75
25
—
15
35
10
—
Write Enable to Clock Setup Time
t_su
5.0
400
170
—
ns
10
200
65
—
15
110
50
—
Write Enable to Clock Release Time
t_rel
5.0
380
160
—
ns
10
180
55
—
15
100
40
—
6. The formulas given are for the typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
V_DD
C_L
f_o
C
D
(f = 1/2 f_o)
REPETITIVE WAVEFORM
D
C
V_DD
V_SS
V_DD
V_SS
50 µF
D ^{Q16 Q32 Q48 Q64}
C
WE
D
C
WE
V_SS
I_D
Q16 Q32 Q48 Q64
C_L C_L C_L C_L
C_L
C_L
C_L
Figure 1. Power Dissipation Test Circuit and Waveform
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