MC14517B Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual 64-Bit Static Shift Register

MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64–bit static shift register consists of two
identical, independent, 64–bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16–bit, 32–bit, and 48–bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
• Diode Protection on All Inputs
• Fully Static Operation
• Output Transitions Occur on the Rising Edge of the Clock Pulse
• Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications
• Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 1.)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
– 0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range – 0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D
Power Dissipation,
per Package (Note 2.)
500
mW
T_A
Operating Temperature Range
– 55 to +125
°C
T_stg
Storage Temperature Range
– 65 to +150
°C
T_L
Lead Temperature
(8–Second Soldering)
260
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v ^{high–impedance circuit. For proper operation, Vin and Vout should be constrained}
to the range V_SS (V_in or V_out) V_DD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14517BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14517B
AWLYYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14517BCP
MC14517BDW
PDIP–16
SOIC–16
2000/Box
47/Rail
MC14517BDWR2 SOIC–16 1000/Tape & Reel
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14517B/D