LC75843UGA Datasheet, PDF (4/35 Pages) ON Semiconductor – Duty General-Purpose LCD Driver

1. When CL is stopped at the low level
LC75843UGA
CE
tL
tH
VIH1
CL
50%
VIL1
tf
tr
VIH1
DI
VIL1
tds
tdh
VIH1
tcp tcs
[Figure 1]
2. When CL is stopped at the high level
CE
VIH1
tL
tH
VIH1
CL
50%
VIL1
tf
DI
tr
tcp tcs
VIH1
VIL1
tds
tdh
[Figure 2]
3. OSCI pin clock timing in external clock operating mode
tCKH
tCKL
OSCI
VIH2
50%
VIL2
1
fCK= _{tCKH + tCKL} [kHz]
DCK=
tCKH
tCKH + tCKL
100[%]
[Figure 3]
VIL1
tch
VIL1
tch
No.A2226-4/35