KAF-16801 Datasheet, PDF (4/16 Pages) ON Semiconductor – Full Frame CCD Image Sensor

KAF−16801
FD. Once the signal has been sampled by the system
electronics, the reset gate (fR) is clocked to remove the
signal and FD is reset to the potential applied by V_RD. More
signal at the floating diffusion reduces the voltage seen at the
output pin. In order to activate the output structure,
an off-chip load must be added to the VOUT pin of the
device – see Figure 3.
Transfer Efficiency Test Pixels and Dummy Pixels
At the beginning of each line and at the end of each line
are extra horizontal CCD pixels. These are a combination of
pixels that are not associated with any vertical CCD register
and two that are associated with extra photo active vertical
CCDs. The two extra photo active vertical CCDs are
provided to give an accurate photo generated signal that can
be used to monitor the charge transfer efficiency in the serial
(horizontal) register.
They are arranged as follows beginning with the first pixel
in each line:
• 11 Dark, Inactive Pixels
• 1 Photoactive Test Pixel
• 3 Inactive Pixels
• 20 Dark Reference Pixels
• 1 Active Buffer Pixel
• 4,096 Photoactive Pixels
• 1 Active Buffer Pixel
• 9 Dark Reference Pixels
• 1 Photoactive Test Pixel
• 2 Inactive Pixels
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the sensor. These photon-induced
electrons are collected locally by the formation of potential
wells at each photogate or pixel site. The number of
electrons collected is linearly dependent on light level and
exposure time and non-linearly dependent on wavelength.
When the pixel’s capacity is reached, excess electrons will
leak into the adjacent pixels within the same column. This
is termed blooming. During the integration period, the fV1
and fV2 register clocks are held at a constant (low) level.
See Figure 8.
Charge Transport
Referring again to Figure 8 − Timing Diagrams,
the integrated charge from each photogate is transported to
the output using a two-step process. Each line (row) of
charge is first transported from the vertical CCDs to the
horizontal CCD register using the fV1 and fV2 register
clocks. The horizontal CCD is presented a new line on the
falling edge of fV1 while fH2 is held high. The horizontal
CCDs then transport each line, pixel by pixel, to the output
structure by alternately clocking the fH1 and fH2 pins in
a complementary fashion. On each falling edge of fH1
a new charge packet is transferred onto a floating diffusion
and sensed by the output amplifier.
Horizontal Register
Output Structure
+15 V
0.1 mF
V_OUT
~5ma
2N3904 or Equivalent
Buffered Output
R1
1 kW
Notes:
1. For operation of up to 10 MHz.
2. The value of R1 depends on the desired output current according the following formula: R1 = 0.7 / I_OUT.
3. The optimal output current depends on the capacitance that needs to be driven by the amplifier and the bandwidth required. 5 mA is
recommended for capacitance of 12 pF and pixel rates up to 20 MHz.
Figure 3. Output Structure Load Diagram
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