CAT5172 Datasheet, PDF (4/10 Pages) ON Semiconductor – 256-Position SPI Compatible Digital Potentiometer

CAT5172
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions (continued)
V_DD = 5 V ±10%, or 3 V ±10%; V_A = V_DD; V_B = 0 V; –40°C < T_A < +85°C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
(Note 2) Max Unit
DYNAMIC CHARACTERISTICS (Notes 7 and 9)
Bandwidth –3 dB
R_AB = 50 kW / 100 kW, Code = 0x80
BW
100/40
kHz
Total Harmonic Distortion
V_A =1 V rms, V_B = 0 V,
f = 1 kHz, R_AB = 10 kW
THD_W
0.05
%
V_W Settling Time (50 kW/100 kW)
V_A = 5 V, V_B = 0 V, ±1 LSB error band
t_S
2
ms
2. Typical specifications represent average readings at +25°C and V_DD = 5 V.
3. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minim-
um resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaran-
teed monotonic.
4. V_AB = V_DD, Wiper (V_W) = no connect.
5. INL and DNL are measured at VW with the DPP configured as a potentiometer divider similar to a voltage output D/A converter. V_A = V_DD
and V_B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
7. Guaranteed by design and not subject to production test.
8. PDISS is calculated from (I_DD x V_DD). CMOS logic level inputs result in minimum power dissipation.
9. All dynamic characteristics use V_DD = 5 V.
Table 5. TIMING CHARACTERISTICS: 50 kW and 100 kW Versions
V_DD = 5 V ± 10%, or 3 V ± 10%; V_A = V_DD; V_B = 0 V; –40°C < T_A < +85°C; unless otherwise noted.
Parameter
Test Conditions
Typ
Symbol Min (Note 10) Max Unit
SPI INTERFACE TIMING CHARACTERISTICS (Notes 11 and 12) (Specifications Apply to All Parts)
Clock Frequency
f_CLK
25 MHz
Input Clock Pulse width
Clock level high or low
t_CH, t_CL
20
ns
Data Setup Time
t_DS
5
ns
Data Hold Time
t_DH
5
ns
CS Setup Time
T_CSS
15
ns
CS High Pulse Width
T_CSW
40
ns
CLK Fall to CS Fall Hold Time
T_CSH0
0
ns
CLK Fall to CS Rise Hold Time
T_CSH1
0
ns
CS Rise to Clock Rise Setup
T_CS1
10
ns
10. Typical specifications represent average readings at +25°C and V_DD = 5 V.
11. Guaranteed by design and not subject to production test.
12. See timing diagram for location of measured values. All input control voltages are specified with t_R = t_F = 2 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V.
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