CAT5172 Datasheet, PDF (3/10 Pages) ON Semiconductor – 256-Position SPI Compatible Digital Potentiometer

CAT5172
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions
V_DD = 5 V ±10%, or 3 V ±10%; V_A = V_DD; V_B = 0 V; –40°C < T_A < +85°C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Typ
Min
(Note 2) Max
Unit
DC CHARACTERISTICS — RHEOSTAT MODE
Resistor Differential Nonlinearity (Note 3)
R_WB, V_A = no connection
R−DNL
−1
Resistor Integral Nonlinearity (Note 3)
R_WB, V_A = no connection
R−INL
−2
Nominal Resistor Tolerance (Note 4)
T_A = 25°C
nR_AB
−20
Resistance Temperature Coefficient
V_AB = V_DD, Wiper = no connection nR_AB/nT
Wiper Resistance
V_DD = 5 V
R_W
V_DD = 3 V
DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE
±0.1
+1
LSB
±0.4
+2
LSB
+20
%
100
ppm/°C
50
120
W
100
250
Resolution
N
8
Bits
Differential Nonlinearity (Note 5)
DNL
−1
±0.1
+1
LSB
Integral Nonlinearity (Note 5)
INL
−1
±0.4
+1
LSB
Voltage Divider Temperature Coefficient
Full−Scale Error
Zero−Scale Error
RESISTOR TERMINALS
Code = 0x80
Code = 0xFF
Code = 0x00
nV_W/nT
V_WFSE
−3
V_WZSE
0
100
ppm/°C
−1
0
LSB
1
3
LSB
Voltage Range (Note 6)
Capacitance (Note 7) A, B
f = 1 MHz, measured to GND,
Code = 0 x 80
V_A,B,W
C_A,B
GND
V_DD
V
45
pF
Capacitance (Note 7) W
f = 1 MHz, measured to GND,
C_W
Code = 0 x 80
60
pF
Common−Mode Leakage (Note 7)
DIGITAL INPUTS
V_A = V_B = V_DD/2
I_CM
1
nA
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance (Note 7)
POWER SUPPLIES
V_DD = 5 V
V_DD = 5 V
V_DD = 3 V
V_DD = 3 V
V_IN = 0 V or 5 V
V_IH
0.7 x V_DD
V
V_IL
0.3V_DD
V
V_IH
0.7 x V_DD
V
V_IL
0.3V_DD
V
I_IL
±1
mA
C_IL
5
pF
Power Supply Range
V_{DD RANGE}
2.7
5.5
V
Supply Current
V_IH = 5 V or V_IL = 0 V
I_DD
0.3
2
mA
Power Dissipation (Note 8)
V_IH = 5 V or V_IL = 0 V, V_DD = 5 V
P_DISS
0.2
mW
Power Supply Sensitivity
nV_DD = +5 V ±10%, Code = Midscale PSS
±0.05 %/%
2. Typical specifications represent average readings at +25°C and V_DD = 5 V.
3. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minim-
um resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaran-
teed monotonic.
4. V_AB = V_DD, Wiper (V_W) = no connect.
5. INL and DNL are measured at VW with the DPP configured as a potentiometer divider similar to a voltage output D/A converter. V_A = V_DD
and V_B = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
7. Guaranteed by design and not subject to production test.
8. PDISS is calculated from (I_DD x V_DD). CMOS logic level inputs result in minimum power dissipation.
9. All dynamic characteristics use V_DD = 5 V.
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