CAT24C64BAC4 Datasheet, PDF (4/9 Pages) ON Semiconductor – 64 Kb I2C CMOS Serial EEPROM 4-ball WLCSP

CAT24C64BC4, CAT24C64BAC4
Power−On Reset (POR)
Each CAT24C64BC4/CAT24C64BAC4 incorporates
Power−On Reset (POR) circuitry which protects the internal
logic against powering up in the wrong state. The device will
power up into Standby mode after V_CC exceeds the POR
trigger level and will power down into Reset mode when
V_CC drops below the POR trigger level. This bi−directional
POR behavior protects the device against ‘brown−out’
failure following a temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
Functional Description
The CAT24C64BC4/CAT24C64BAC4 supports the
Inter−Integrated Circuit (I²C) Bus protocol. The protocol
relies on the use of a Master device, which provides the clock
and directs bus traffic, and Slave devices which execute
requests. The CAT24C64BC4/CAT24C64BAC4 operates
as a Slave device. Both Master and Slave can transmit or
receive, but only the Master can assign those roles.
I²C Bus Protocol
The 2−wire I²C bus consists of two lines, SCL and SDA,
connected to the V_CC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address
(Figure 3). The first 4 bits of the Slave address are set to
1010. The next 3 bits are set to 0 0 0 ( CAT24C64BC4) or to
1 0 0 (CAT24C64BAC4). The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is to be performed.
Acknowledge
During the 9^th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
Figure 2. Start/Stop Timing
STOP
CONDITION
1 0 1 0 0 0 0 R/W CAT24C64BC4
1 0 1 0 1 0 0 R/W CAT24C64BAC4
Figure 3. Slave Address Bits
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