MT9M024 Datasheet, PDF (35/65 Pages) ON Semiconductor – CMOS Digital Image Sensor

MT9M024: 1/3-Inch CMOS Digital Image Sensor
Features
Embedded Data
The embedded data contains the configuration of the image being displayed. This
includes all register settings used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1: Registers R0x3000 to R0x312F
Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
Note: All non-defined registers will have a value of 0.
In parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register
data will be transferred over 2 pixels where the register data will be broken up into 8msb
and 8lsb. The alignment of the 8bit data will be on the 8MSB bits of the 12-bit pixel word.
For example, if a register value of 0x1234 is to be transmitted, it will be transmitted over
2, 12-bit pixels as follows: 0x120, 0x340.
The first pixel of each line in the embedded data is a tag value of 0x0A0. This signifies
that all subsequent data is 8 bit data aligned to the MSB of the 12-bit pixel.
The figure below summarizes how the embedded data transmission looks like. It should
be noted that data, as shown in Figure 22, is aligned to the MSB of each word:
Figure 22: Format of Embedded Data Output within a Frame
Data line 1
data_format_
code =8'h0A
8'hAA
{register_
address_MSB}
8'hA5
{register_
address_LSB}
{register_
value_LSB}
8'h5A
8'h5A
{register_
value_MSB}
8'h5A
Data line 2
data_format_
code =8'h0A
8'hAA
{register_
address_MSB}
{register_
value_LSB}
8'hA5
8'h5A
{register_
address_LSB}
8'h5A
{register_
value_MSB}
8'h5A
The data embedded in these rows are as follows:
• 0x0A0 - identifier
• 0xAA0
• Register Address MSB of the first register
• 0xA50
• Register Address LSB of the first register
• 0x5A0
• Register Value MSB of the first register addressed
• 0x5A0
• Register Value LSB of the first register addressed
• 0x5A0
• Register Value MSB of the register at first address + 2
• 0x5A0
• Register Value LSB of the register at first address + 2
• 0x5A0
• etc.
MT9M024_DS Rev. G Pub. 4/15 EN
35
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