NSS40400CF8T1G Datasheet, PDF (3/4 Pages) ON Semiconductor – 40 V, 7 A, Low VCE(sat) PNP Transistor

NSS40400CF8T1G
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE F
A
M
8765
S
B
1234
L
D
J
G
C
0.05 (0.002)
K
5678
4321
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. COLLECTOR
4. BASE
5. EMITTER
6. COLLECTOR
7. COLLECTOR
8. COLLECTOR
0.457
0.018
2.032
0.08
SOLDERING FOOTPRINT*
0.635
0.025
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED
0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET
IN HORIZONTAL AND VERTICAL SHALL
NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF
MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP
AND BOTTOM LEAD SURFACE.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 2.95 3.10 0.116 0.122
B 1.55 1.70 0.061 0.067
C 1.00 1.10 0.039 0.043
D 0.25 0.35 0.010 0.014
G
0.65 BSC
0.025 BSC
J 0.10 0.20 0.004 0.008
K 0.28 0.42 0.011 0.017
L
0.55 BSC
0.022 BSC
M 5 ° NOM
5 ° NOM
S 1.80 2.00 0.072 0.080
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028
Basic
ǒ Ǔ _{SCALE 20:1}
mm
inches
0.457
0.018
0.66
0.026
0.711
0.028
Style 4
0.178
0.007
ǒ Ǔ _{SCALE 20:1}
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
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