MMBF5484LT1 Datasheet, PDF (3/10 Pages) Motorola, Inc – JFET Transistor

MMBF5484LT1
INPUT
TO 50 Ω
SOURCE
NEUTRALIZING
COIL
L1
C1
C5
Rg′ L3
C6
C2
VGS
C3
C4
L2
CASE
C7
TO 500 Ω
LOAD
COMMON
VDS
+15 V
ID = 5.0 mA
Adjust VGS for
ID = 50 mA
VGS < 0 Volts
NOTE:
The noise source is a hot–cold body
(AIL type 70 or equivalent) with a
test receiver (AIL type 136 or equivalent).
Reference
Designation
C1
C2
C3
C4
C5
C6
C7
L1
L2
L3
VALUE
100 MHz 400 MHz
7.0 pF
1.8 pF
1000 pF
17 pF
3.0 pF
1.0 pF
1–12 pF 0.8–8.0 pF
1–12 pF 0.8–8.0 pF
0.0015 µF 0.001 µF
0.0015 µF 0.001 µF
3.0 µH*
0.2 µH**
0.15 µH* 0.03 µH**
0.14 µH* 0.022 µH**
*L1 17 turns, (approx. — depends upon circuit layout) AWG #28
enameled copper wire, close wound on 9/32″ ceramic coil
form. Tuning provided by a powdered iron slug.
*L2 4–1/2 turns, AWG #18 enameled copper wire, 5/16″ long,
3/8″ I.D. (AIR CORE).
*L3 3–1/2 turns, AWG #18 enameled copper wire, 1/4″ long,
3/8″ I.D. (AIR CORE).
**L1 6 turns, (approx. — depends upon circuit layout) AWG #24
enameled copper wire, close wound on 7/32″ ceramic coil
form. Tuning provided by an aluminum slug.
**L2 1 turn, AWG #16 enameled copper wire, 3/8″ I.D.
(AIR CORE).
**L3 1/2 turn, AWG #16 enameled copper wire, 1/4″ I.D.
(AIR CORE).
Figure 2. 100 MHz and 400 MHz Neutralized Test Circuit
10
8.0
6.0
f = 400 MHz
4.0
NOISE FIGURE
(Tchannel = 25°C)
6.5
ID = 5.0 mA
5.5
4.5
3.5
f = 400 MHz
VDS = 15 V
VGS = 0 V
2.0
100 MHz
0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VDS, DRAIN–SOURCE VOLTAGE (VOLTS)
Figure 3. Effects of Drain–Source Voltage
2.5
100 MHz
1.5
0
2.0
4.0
6.0
8.0
10
12
14
ID, DRAIN CURRENT (mA)
Figure 4. Effects of Drain Current
INTERMODULATION CHARACTERISTICS
+ 40
+ 20
0
VDS = 15 Vdc
f1 = 399 MHz
– 20
f2 = 400 MHz
– 40
3RD ORDER INTERCEPT
– 60
– 80
– 100
– 120
– 140
– 160
– 120
FUNDAMENTAL
OUTPUT @ IDSS,
0.25 IDSS
3RD ORDER IMD
OUTPUT @ IDSS,
0.25 IDSS
– 100 – 80 – 60 – 40 – 20 0 + 20
Pin, INPUT POWER PER TONE (dB)
Figure 5. Third Order Intermodulation Distortion
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3