MC74HC73A_16 Datasheet, PDF (3/7 Pages) ON Semiconductor – Dual J-K Flip-Flop with Reset

MC74HC73A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns)
Symbol
f_max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
t_PLH,
t_PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
t_PLH,
t_PHL
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
C_in
Maximum Input Capacitance
Guaranteed Limit
V_CC
– 55 to
V
25_C v 85_C v 125_C _Unit
2.0
6.0
4.8
4.0
MHz
4.5
30
24
20
6.0
35
28
24
2.0
125
155
190
ns
4.5
25
31
38
6.0
21
26
32
2.0
155
195
235
ns
4.5
31
39
47
6.0
26
33
40
2.0
75
4.5
15
6.0
13
95
110
ns
19
22
16
19
—
10
10
10
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD
Power Dissipation Capacitance (Per Flip−Flop)*
35
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
TIMING REQUIREMENTS (Input t_r = t_f = 6 ns)
Symbol
t_su
Parameter
Minimum Setup Time, J or K to Clock
(Figure 3)
t_h
Minimum Hold Time, Clock to J or K
(Figure 3)
t_rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
t_w
Minimum Pulse Width, Clock
(Figure 1)
t_w
Minimum Pulse Width, Reset
(Figure 2)
t_r, t_f
Maximum Input Rise and Fall Times
(Figure 1)
Guaranteed Limit
V_CC
– 55 to
V
25_C v 85_C v 125_C _Unit
2.0
100
125
150
ns
4.5
20
25
30
6.0
17
21
26
2.0
3
3
3
ns
4.5
3
3
3
6.0
3
3
3
2.0
100
125
150
ns
4.5
20
25
30
6.0
17
21
26
2.0
80
4.5
16
6.0
14
100
120
ns
20
24
17
20
2.0
80
4.5
16
6.0
14
100
120
ns
20
24
17
20
2.0
1000
1000
1000
ns
4.5
500
500
500
6.0
400
400
400
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