MC74HC573A_14 Datasheet, PDF (3/7 Pages) ON Semiconductor – Octal 3-State Noninverting Transparent Latch

MC74HC573A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
t_PLH,
t_PHL
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
V_CC
Guaranteed Limit
V –55 to 25_C v85_C v125_C Unit
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
140
180
38
45
33
38
t_PLH,
t_PHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
160
3.0
105
4.5
32
6.0
27
200
240
ns
145
190
40
48
34
41
t_PLZ,
t_PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
t_PZL,
t_PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
60
3.0
27
4.5
12
6.0
10
75
90
ns
32
36
15
18
13
15
C_in Maximum Input Capacitance
C_out Maximum 3−State Output Capacitance (Output in High−Impedance State)
10
10
10
pF
15
15
15
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Enabled Output)*
23
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
TIMING REQUIREMENTS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
Parameter
t_su Minimum Setup Time, Input D to Latch Enable
t_h
Minimum Hold Time, Latch Enable to Input D
t_w
Minimum Pulse Width, Latch Enable
t_r, t_f Maximum Input Rise and Fall Times
V_CC
Figure V
4
2.0
3.0
4.5
6.0
4
2.0
3.0
4.5
6.0
2
2.0
3.0
4.5
6.0
1
2.0
3.0
4.5
6.0
Guaranteed Limit
–55 to 25_C
v85_C
v125_C
Min Max Min Max Min Max Unit
50
65
75
ns
40
50
60
10
13
15
9.0
11
13
5.0
5.0
5.0
ns
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
75
95
110
ns
60
80
90
15
19
22
13
16
19
1000
800
500
400
1000
800
500
400
1000 ns
800
500
400
http://onsemi.com
3