MC74HC573A_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – Octal 3-State Noninverting Transparent Latch

MC74HC573A
Octal 3-State Noninverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 218 FETs or 54.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0 ²
D1 ³
D2 ⁴
D3 ⁵
D4 ⁶
D5 ⁷
D6 ⁸
D7 ⁹
19 _Q0
18 _Q1
17 _Q2
16 _Q3
15 _Q4
14 _Q5
13 _Q6
12 _Q7
NONINVERTING
OUTPUTS
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
PIN 20 = V_CC
PIN 10 = GND
Design Criteria
Internal Gate Count*
Value
54.5
Internal Gate Progation Delay
1.5
Internal Gate Power Dissipation
5.0
Speed Power Product
0.0075
*Equivalent to a two−input NAND gate.
Units
ea.
ns
mW
pJ
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 16
http://onsemi.com
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
OUTPUT
ENABLE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20
V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LATCH
ENABLE
MARKING DIAGRAMS
20
74HC573A
AWLYYWWG
20
HC
573A
ALYWG
G
1
1
SOIC−20
TSSOP−20
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output Latch
Enable Enable D
Output
Q
L
H
H
L
H
L
L
L
X
H
X
X
X = Don’t Care
Z = High Impedance
H
L
No Change
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74HC573A/D