MC74HC4051A_06 Datasheet, PDF (3/18 Pages) ON Semiconductor – Analog Multiplexers / Demultiplexers

MC74HC4051A, MC74HC4052A, MC74HC4053A
LOGIC DIAGRAM
MC74HC4053A
Triple Single−Pole, Double−Position Plus Common Off
X0 ¹²
X1 ¹³
X SWITCH
14 _X
ANALOG
INPUTS/OUTPUTS
Y0 ²
Y1 ¹
Z0 ⁵
Z1 ³
A ¹¹
CHANNEL-SELECT
INPUTS
B ¹⁰
C⁹
ENABLE ⁶
Y SWITCH
Z SWITCH
15 _Y
COMMON
OUTPUTS/INPUTS
4_Z
PIN 16 = V_CC
PIN 7 = V_EE
PIN 8 = GND
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
FUNCTION TABLE − MC74HC4053A
Control Inputs
Enable
Select
CBA
ON Channels
L
L L L Z0 Y0 X0
L
L L H Z0 Y0 X1
L
L H L Z0 Y1 X0
L
L H H Z0 Y1 X1
L
H L L Z1 Y0 X0
L
H L H Z1 Y0 X1
L
H H L Z1 Y1 X0
L
H H H Z1 Y1 X1
H
XXX
NONE
X = Don’t Care
Pinout: MC74HC4053A (Top View)
V_CC Y X X1 X0 A B C
16 15 14 13 12 11 10 9
12345678
Y1 Y0 Z1 Z Z0 Enable V_EE GND
MAXIMUM RATINGS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0}
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Referenced to VEE) – 0.5 to + 14.0}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VEE Negative DC Supply Voltage (Referenced to GND)}
– 7.0 to + 5.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VIS Analog Input Voltage}
V_EE − 0.5 to
V
V_CC + 0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Vin ^{Digital Input Voltage (Referenced to GND)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^I
DC Current, Into or Out of Any Pin
– 0.5 to V_CC + 0.5 V
± 25
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^PD ^{Power Dissipation in Still Air,}
Plastic DIP†
750
mW
EIAJ/SOIC Package†
500
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{TSSOP Packageâ€} 
450
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Tstg Storage Temperature Range}
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{TL Lead Temperature, 1 mm from Case for 10 Seconds}
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Plastic DIP, SOIC or TSSOP Package}
260
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Maximum ratings are those values beyond which device damage can occur. Maximum ratings}
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V_in and
V_out should be constrained to the
range GND v (V_in or V_out) v V_CC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V_CC).
Unused outputs must be left open.
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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