MC74HC174A Datasheet, PDF (3/8 Pages) ON Semiconductor – Hex D Flip-Flop with Common Clock and Reset

MC74HC174A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _ICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _NOTES:
Parameter
Test Conditions
Maximum Input Leakage Current Vin = VCC or GND
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
VCC
V
6.0
6.0
Guaranteed Limit
– 55 to
25_C
v v 85_C
125_C
Unit
± 0.1
± 1.0
± 1.0
µA
4.0
40
160
µA
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + S∆ICC.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
VCC
V
Guaranteed Limit
– 55 to
25_C
v v 85_C
125_C
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
6.0
4.8
4.0
MHz
4.5
30
24
20
6.0
35
28
24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
2.0
110
140
165
ns
4.5
22
28
33
6.0
19
24
28
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Reset to Q
(Figures 2 and 4)
2.0
110
140
160
ns
4.5
21
28
32
6.0
19
24
27
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
75
4.5
15
6.0
13
95
110
ns
19
22
16
19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Maximum Input Capacitance
10
10
10
pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON}
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
62
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Guaranteed Limit
VCC ^{– 55 to 25_C}
v 85_C
v 125_C
Fig.
V
Min Max Min Max Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tsu MinimumSetupTime,DatatoClock}
3
2.0
50
65
75
ns
4.5
10
13
15
6.0 9.0
11
13
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Clock to Data
3
2.0 5.0
5.0
5.0
ns
4.5 5.0
5.0
5.0
6.0 5.0
5.0
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{trec Minimum Recovery Time, Reset Inactive to}
2
2.0 5.0
5.0
5.0
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Clock
4.5 5.0
5.0
5.0
6.0 5.0
5.0
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tw MinimumPulseWidth,Clock}
1
2.0
75
95
110
ns
4.5
15
19
22
6.0
13
16
19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tw MinimumPulseWidth,Reset}
2
2.0
75
95
110
ns
4.5
15
19
22
6.0
13
16
19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tr,tf MaximumInputRiseandFallTimes}
1
2.0
4.5
6.0
1000
500
400
1000
500
400
1000 ns
500
400
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