MC74HC174A Datasheet, PDF (1/8 Pages) ON Semiconductor – Hex D Flip-Flop with Common Clock and Reset

MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active–low.
• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 ³
D1 ⁴
D2 ⁶
D3 ¹¹
D4 ¹³
D5 ¹⁴
2 _Q0
5 _Q1
7 _Q2
10 _Q3
12 _Q4
15 _Q5
NONINVERTING
OUTPUTS
CLOCK ⁹
RESET ¹
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Output
Reset Clock D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X No Change
H
X No Change
ÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
Value Units
ÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
40.5 ea.
ÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
µW
ÎÎÎÎÎÎÎÎÎÎÎÎÎ Speed Power Product
.0075 pJ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ *Equivalent to a two–input NAND gate.
16
1
16
1
http://onsemi.com
PDIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
MC74HC174AN
AWLYYWW
1
16
HC174A
AWLYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
RESET 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CLOCK
ORDERING INFORMATION
Device
Package Shipping
MC74HC174AN
PDIP–16 2000 / Box
MC74HC174AD
SOIC–16 48 / Rail
MC74HC174ADR2
SOIC–16 2500 / Reel
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 7
Publication Order Number:
MC74HC174A/D