MC74AC161_15 Datasheet, PDF (3/12 Pages) ON Semiconductor – Synchronous Presettable Binary Counter

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PE
′161 ′163
CEP
CET
′163
ONLY
P₀
P₁
P₂
P₃
TC
CP
CP ′161
CP
ONLY
D CP D
C_{D Q Q}
Q₀
Q₀
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR ′161
SR ′163
Q₀
Q₁
Q₂
Q₃
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 4. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V_CC
V_I
V_O
I_IK
I_OK
I_O
I_CC
I_GND
T_STG
T_L
T_J
q_JA
P_D
MSL
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink/Source Current
DC Supply Current per Output Pin
DC Ground Current per Output Pin
Storage Temperature Range
Lead temperature, 1 mm from Case for 10 Seconds
Junction temperature under Bias
Thermal Resistance (Note 2)
Power Dissipation in Still Air at 65°C (Note 3)
Moisture Sensitivity
(Note 1)
*0.5 to )7.0
*0.5 v V_I v V_CC )0.5
*0.5 v V_O v V_CC )0.5
$20
$50
$50
$50
$50
*65 to )150
260
)150
69.1
500
Level 1
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
F_R
V_ESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
Human Body Model (Note 4)
> 2000
V
Machine Model (Note 5)
> 200
Charged Device Model (Note 6)
> 1000
I_{Latch−Up} Latch−Up Performance Above V_CC and Below GND at 85°C (Note 7)
$100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I_O absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD51−7.
3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C.
4. Tested to EIA/JESD22−A114−A.
5. Tested to EIA/JESD22−A115−A.
6. Tested to JESD22−C101−A.
7. Tested to EIA/JESD78.
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