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MC14555B_06 Datasheet, PDF (3/6 Pages) ON Semiconductor – Dual Binary to 1−of−4 Decoder/Demultiplexer
MC14555B, MC14556B
ÎÎÎÎSWÎÎITCÎÎHINÎÎG CÎÎHARÎÎACÎÎTERÎÎISTÎÎICSÎÎ(NoÎÎte 5ÎÎ) (CÎÎL = 5ÎÎ0 pFÎÎ, TAÎÎ= 25ÎΰC)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTyÎÎp ÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic
Symbol
VDD
Min
(Note 6)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
−
100
200
10
−
50
100
15
−
40
80
Propagation Delay Time − A, B to Output
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
tPLH,
ns
tPHL
5.0
−
220
440
10
−
95
190
15
−
70
140
Propagation Delay Time − E to Output
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
ns
tPHL
5.0
−
200
400
10
−
85
170
15
−
65
130
5. The formulas given are for the typical characteristics only at 25°C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
20 ns
20 ns
90%
VDD
50%
A INPUTS
1
10%
VSS
(50% DUTY CYCLE)
2f
VDD
B INPUTS
VSS
(50% DUTY CYCLE)
VOH
OUTPUT Q1
VOL
All 8 outputs connect to respective CL loads.
f in respect to a system clock.
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
INPUT A HIGH, INPUT E LOW
20 ns
INPUT B
tPHL
OUTPUT Q3
MC14556B
tTHL
tPLH
OUTPUT Q3
MC14555B
tTLH
90%
50%
10%
90%
50%
10%
90%
50%
10%
VDD
VSS
tPLH
VOH
tTLH VOL
tPHL
VOH
VOL
tTHL
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
A
B
E
*Eliminated for MC14555B
http://onsemi.com
3
*
Q0
*
Q1
*
Q2
*
Q3