MC14555B_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual Binary to 1−of−4 Decoder/Demultiplexer

MC14555B, MC14556B
Dual Binary to 1−of−4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
Features
• Diode Protection on All Inputs
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out − 0.5 to V_DD V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
per Pin
± 10
mA
Power Dissipation, per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
1
1
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC1455xBCP
AWLYYWWG
SOIC−16 ¹⁶
D SUFFIX
CASE 751B
1
1455xBG
AWLYWW
16
SOEIAJ−16
F SUFFIX
CASE 966
MC1455xB
ALYWG
1
1
x
= 5 or 6
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
PIN ASSIGNMENTS
MC14555B
MC14556B
E_A 1
A_A 2
B_A 3
Q0_A 4
Q1_A 5
Q2_A 6
Q3_A 7
V_SS 8
16 V_DD E_A 1
15 E_B
A_A 2
14 A_B
B_A 3
13 B_B Q0_A 4
12 Q0_B Q1_A 5
11 Q1_B Q2_A 6
10 Q2_B Q3_A 7
9 Q3_B V_SS 8
16 V_DD
15 E_B
14 A_B
13 B_B
12 Q0_B
11 Q1_B
10 Q2_B
9 Q3_B
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 8
Publication Order Number:
MC14555B/D