CM3212 Datasheet, PDF (3/11 Pages) ON Semiconductor – VTT Termination Voltage Regulator

CM3212
PACKAGE / PINOUT DIAGRAMS
Pin 1
Marking
VIN
Top View
(Pins Down View)
1
8
Thermal Pad
VDDQ
VTT 2
7 EN_VTT
NC 3
6 ADJSD
GND 4
5 VREF
8−Lead WDFN Package
CM3212−02DE
Top View
(Pins Down View)
VIN
VTT
NC
GND
1
8
2
7
3
6
4
5
8−Lead SOIC Package
CM3212−02SM
VDDQ
EN_VTT
ADJSD
VREF
Table 1. PIN DESCRIPTIONS
Pin(s)
Name
Description
1
VIN
Input supply voltage pin. Bypass with a 220 mF capacitor to GND.
2
VTT
V_TT regulator output pin, which is preset to 50% of V_DDQ.
3
NC
Not internally connected. For better heat flow, connect to GND (exposed pad).
4
GND
Ground pin.
5
VREF
Reference voltage output pin. This pin buffers internal reference of V_DDQ/2. Bypass with 0.1 mF ceramic to
GND. It is available as long as V_DDQ is enabled. During Manual Shutdown or Thermal Shutdown, it is tied to
GND.
6
ADJSD This pin is for V_DDQ output voltage adjustment. It is available as long as V_DDQ is enabled. During Manual/
Thermal shutdown, it is tightened to GND. The V_DDQ output voltage is set
using an external resistor divider connected to ADJSD:
V_DDQ = 1.25 V × ((R1 + R2) / R2)
7
8
EPad
EN_VTT
VDDQ
GND
Where R1 is the upper resistor and R2 is the ground−side resistor. In addition, the ADJSD pin functions as a
Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode. When
ADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low−leakage Schottky diode
in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting.
Enable pin for V_TT regulator (it is internally pulled “high”). A logic HIGH on this pin enables the V_TT output,
and a logic LOW on this pin tri−states the V_TT output.
VDDQ regulator output voltage pin.
The backside exposed pad which serves as the package heatsink. Must be connected to GND.
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