CM2020-01TR Datasheet, PDF (3/12 Pages) ON Semiconductor – HDMI Transmitter Port Protection and Interface Device

CM2020-01TR
PIN DESCRIPTIONS
PINS
4, 35
6, 33
7, 32
9, 30
10, 29
12, 27
13, 26
15, 24
16
23
17
22
18
21
19
20
2
1
38
37
3, 36
5, 34, 8, 31,
11, 28, 14,
25
NAME
TMDS_D2+
TMDS_D2–
TMDS_D1+
TMDS_D1–
TMDS_D0+
TMDS_D0–
TMDS_CK+
TMDS_CK–
CE_REMOTE_IN
CE_REMOTE_OUT
DDC_CLK_IN
DDC_CLK_OUT
DDC_DAT_IN
DDC_DAT_OUT
HOTPLUG_DET_IN
HOTPLUG_DET_OUT
LV_SUPPLY
5V_SUPPLY
5V_OUT
ESD_BYP
GND
TMDS_GND
ESD Level DESCRIPTION
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
8kV²
TMDS 0.9pF ESD protection.¹
2kV³
LV_SUPPLY referenced logic level into ASIC.
8kV²
2kV³
5V_SUPPLY referenced logic level out plus 3.5pF ESD to
connector.
LV_SUPPLY referenced logic level into ASIC.
8kV²
2kV³
5V_SUPPLY referenced logic level out plus 3.5pF ESD to
connector.
LV_SUPPLY referenced logic level into ASIC.
8kV²
2kV³
5V_SUPPLY referenced logic level out plus 3.5pF ESD to
connector.
LV_SUPPLY referenced logic level into ASIC.
8kV²
2kV³
5V_SUPPLY referenced logic level out plus 3.5pF ESD to
connector.
Bias for CE / DDC / HOTPLUG level shifters.
2kV³
Current source for 5V_OUT.
8kV²
2kV³
N/A
N/A
55mA minimum overcurrent protected 5V output. This output must
be bypassed with a 0.1 F ceramic capacitor.
This pin may be connected to a 0.1 F ceramic capacitor, but it is not
necessary.
Supply GND reference.
TMDS ESD and Parasitic GND return.⁴
Note 1: These 2 pins need to be connected together in-line on the PCB.
Note 2: Standard IEC 61000-4-2, C_DISCHARGE=150pF, Ω R_DISCHARGE=330 , 5V_SUPPLY and LV_SUPPLY within recommended
operating conditions, GND=0V, 5V_OUT (pin 38), each bypassed with a 0.1µF ceramic capacitor connected to GND.
Note 3: Human Body Model per MIL-STD-883, Method 3015, C_DISCHARGE=100pF, Ω R_DISCHARGE=1.5k , 5V_SUPPLY and LV_SUPPLY
within recommended operating conditions, GND=0V and 5V_OUT (pin 38), and each bypassed with a 0.1µF ceramic
capacitor connected to GND.
Note 4: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at
the connector.
Rev. 4 | Page 3 of 12 | www.onsemi.com