CAV93C56 Datasheet, PDF (3/10 Pages) ON Semiconductor – 2 Kb Microwire Serial CMOS EEPROM

CAV93C56
Table 5. A.C. CHARACTERISTICS (Note 5)
(V_CC = +2.5V to +5.5V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
t_CSS
t_CSH
t_DIS
t_DIH
t_PD1
t_PD0
t_HZ (Note 6)
t_EW
t_CSMIN
t_SKHI
t_SKLOW
t_SV
SK_MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
Limits
Min
50
0
100
100
0.25
0.25
0.25
DC
Max
0.25
0.25
100
5
0.25
2000
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ 50 ns
0.4 V to 2.4 V
4.5 V v V_CC v 5.5 V
0.8 V, 2.0 V
4.5 V v V_CC v 5.5 V
0.2 V_CC to 0.7 V_CC
2.5 V v V_CC v 4.5 V
0.5 V_CC
2.5 V v V_CC v 4.5 V
Current Source I_OLmax/I_OHmax; CL=100 pF
Table 7. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Max
Units
t_PUR
Power−up to Read Operation
1
ms
t_PUW
Power−up to Write Operation
1
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
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