CAT93C46R Datasheet, PDF (3/13 Pages) Catalyst Semiconductor – 1-Kb Microwire Serial EEPROM

CAT93C46R
Table 4. PIN CAPACITANCE
Symbol
Test
Conditions
Min
Typ
Max Units
C_OUT (Note 4) Output Capacitance (DO)
V_OUT = 0 V
5
pF
C_IN (Note 4)
Input Capacitance (CS, SK, DI, ORG)
V_IN = 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS (Note 5)
V_CC = 1.8 V − 5.5 V
V_CC = 4.5 V − 5.5 V
Symbol
Parameter
Min
Max
Min
Max
Units
t_CSS
CS Setup Time
50
50
ns
t_CSH
CS Hold Time
0
0
ns
t_DIS
DI Setup Time
100
50
ns
t_DIH
DI Hold Time
100
50
ns
t_PD1
Output Delay to 1
0.25
0.1
ms
t_PD0
Output Delay to 0
0.25
0.1
ms
t_HZ (Note 6)
Output Delay to High−Z
100
100
ns
t_EW
Program/Erase Pulse Width
5
5
ms
t_CSMIN
Minimum CS Low Time
0.25
0.1
ms
t_SKHI
Minimum SK High Time
0.25
0.1
ms
t_SKLOW
Minimum SK Low Time
0.25
0.1
ms
t_SV
Output Delay to Status Valid
0.25
0.1
ms
SK_MAX
Maximum Clock Frequency
DC
2
DC
4
MHz
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. POWER−UP TIMING (Notes 4 and 7)
Symbol
Parameter
Max
t_PUR
Power−up to Read Operation
1
t_PUW
Power−up to Write Operation
1
7. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Units
ms
ms
Table 7. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
v 50 ns
0.4 V to 2.4 V
4.5 V v V_CC v 5.5 V
0.8 V, 2.0 V
4.5 V v V_CC v 5.5 V
0.2 V_CC to 0.7 V_CC
1.8 V v V_CC v 4.5 V
0.5 V_CC
1.8 V v V_CC v 4.5 V
Current Source I_OLmax/I_OHmax; C_L = 100 pF
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