CAT24M01_1110 Datasheet, PDF (3/14 Pages) ON Semiconductor – 1 Mb I2C CMOS Serial EEPROM

CAT24M01
Table 4. PIN IMPEDANCE CHARACTERISTICS
V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4)
SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
C_IN (Note 4)
Input Capacitance (other pins)
V_IN = 0 V
6
pF
I_WP, I_A (Note 5)
WP Input Current, Address Input Current (A₁, A₂)
V_IN < V_IH, V_CC = 5.5 V
75
mA
V_IN < V_IH, V_CC = 3.3 V
50
V_IN < V_IH, V_CC = 1.8 V
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A₁, A₂ pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS (Note 6)
V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.
Standard
V_CC = 1.8 V − 5.5 V
Fast
V_CC = 1.8 V − 5.5 V
Fast−Plus
V_CC = 2.5 V − 5.5 V
T_A = −405C to +855C
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
F_SCL
Clock Frequency
100
400
1,000
kHz
t_HD:STA
START Condition Hold Time
4
0.6
0.25
ms
t_LOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
t_HIGH
High Period of SCL Clock
4
0.6
0.40
ms
t_SU:STA
START Condition Setup Time
4.7
0.6
0.25
ms
t_HD:DAT
Data In Hold Time
0
0
0
ms
t_SU:DAT
Data In Setup Time
250
100
50
ns
t_R (Note 7)
SDA and SCL Rise Time
1,000
300
100
ns
t_F (Note 7)
SDA and SCL Fall Time
300
300
100
ns
t_SU:STO
STOP Condition Setup Time
4
0.6
0.25
ms
t_BUF
Bus Free Time Between
4.7
1.3
0.5
ms
STOP and START
t_AA
SCL Low to Data Out Valid
3.5
0.9
0.40
ms
t_DH
Data Out Hold Time
50
50
50
ns
T_i (Note 7)
Noise Pulse Filtered at SCL
50
50
50
ns
and SDA Inputs
t_SU:WP
WP Setup Time
0
0
0
ms
t_HD:WP
WP Hold Time
2.5
2.5
1
ms
t_WR
Write Cycle Time
5
5
5
ms
t_PU (Notes 7, 8) Power-up to Ready Mode
0.1
0.1
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t_PU is the delay between the time V_CC is stable and the device is ready to accept commands.
0.1
ms
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x V_CC to 0.8 x V_CC
≤ 50 ns
Input Reference Levels
Output Reference Levels
Output Load
0.3 x V_CC, 0.7 x V_CC
0.5 x V_CC
Current Source: I_L = 3 mA (V_CC ≥ 2.5 V); I_L = 1 mA (V_CC < 2.5 V); C_L = 100 pF
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