CAT24C32_15 Datasheet, PDF (3/16 Pages) ON Semiconductor – 32-Kb I2C CMOS Serial EEPROM

CAT24C32
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V_CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V_CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
N_END (Note 3) Endurance
1,000,000
Program/Erase Cycles
T_DR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V_CC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C and V_CC = 1.7 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
I_CCR
Read Current
Read, f_SCL = 400 kHz
1
mA
I_CCW
Write Current
Write, f_SCL = 400 kHz
2
mA
I_SB
Standby Current
All I/O Pins at GND or V_CC
T_A = −40°C to +85°C
V_CC ≤ 3.3 V
1
mA
T_A = −40°C to +85°C
3
V_CC > 3.3 V
T_A = −40°C to +125°C
5
I_L
I/O Pin Leakage
Pin at GND or V_CC
2
mA
V_IL
Input Low Voltage
−0.5
V_CC x 0.3
V
V_IH
Input High Voltage
SCL, SDA Inputs
V_CC x 0.7
6.5
V
WP, A0, A1, A2 Inputs
V_CC x 0.7
V_CC + 0.5
V_OL1
Output Low Voltage
V_CC ≥ 2.5 V, I_OL = 3.0 mA
0.4
V
V_OL2
Output Low Voltage
V_CC < 2.5 V, I_OL = 1.0 mA
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +125°C and V_CC = 1.7 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4) SDA I/O Pin Capacitance
V_IN = 0 V, T_A = 25°C, f = 1.0 MHz
8
pF
C_IN (Note 4) Input Capacitance (other pins)
V_IN = 0 V, T_A = 25°C, f = 1.0 MHz
6
pF
I_WP (Note 5) WP Input Current
V_IN < V_IH, V_CC = 5.5 V
130
mA
V_IN < V_IH, V_CC = 3.3 V
120
V_IN < V_IH, V_CC = 1.7 V
80
V_IN > V_IH
2
I_A (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
V_IN < V_IH, V_CC = 1.7 V
50
mA
35
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
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