CAT24C03 Datasheet, PDF (3/14 Pages) Catalyst Semiconductor – 2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection

CAT24C03, CAT24C05
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4)
SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
I_WP (Note 5)
Input Capacitance (Other Pins)
WP Input Current
V_IN = 0 V
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
6
pF
200
mA
150
V_IN < V_IH, V_CC = 1.8 V
100
V_IN > V_IH
1
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS
(Note 6) (V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Standard
Symbol
Parameter
Min
Max
F_SCL
Clock Frequency
t_HD:STA
START Condition Hold Time
4
t_LOW
Low Period of SCL Clock
4.7
t_HIGH
High Period of SCL Clock
4
t_SU:STA
START Condition Setup Time
4.7
t_HD:DAT
Data In Hold Time
0
t_SU:DAT
Data In Setup Time
250
t_R
SDA and SCL Rise Time
t_F (Note 7)
SDA and SCL Fall Time
t_SU:STO
STOP Condition Setup Time
4
t_BUF
Bus Free Time Between STOP and START
4.7
t_AA
SCL Low to Data Out Valid
t_DH
Data Out Hold Time
100
T_i (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
t_SU:WP
WP Setup Time
0
t_HD:WP
WP Hold Time
2.5
t_WR
Write Cycle Time
t_PU (Notes 7, 8) Power−up to Ready Mode
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t_PU is the delay between the time V_CC is stable and the device is ready to accept commands.
100
1000
300
3.5
100
5
1
Fast
Min
Max
400
0.6
1.3
0.6
0.6
0
100
300
300
0.6
1.3
0.9
100
100
0
2.5
5
1
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
0.2 x V_CC to 0.8 x V_CC
v 50 ns
Input Reference Levels
0.3 x V_CC, 0.7 x V_CC
Output Reference Levels
Output Load
0.5 x V_CC
Current Source: I_OL = 3 mA (V_CC w 2.5 V); I_OL = 1 mA (V_CC < 2.5 V); C_L = 100 pF
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