NOIV1SN1300A Datasheet, PDF (28/76 Pages) ON Semiconductor – VITA 1300 1.3 Megapixel 150 FPS Global Shutter CMOS Image Sensor

NOIV1SN1300A, NOIV2SN1300A
Serial Peripheral Interface
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 16 shows the communication protocol for read and
write accesses of the SPI registers. The VITA 1300 sensor
uses 9-bit addresses and 16-bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high-Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the
9-bit data is transferred, most significant bit first.
The sck clock is passed through to the sensor as
indicated in Figure 16. The sensor samples this
data on a rising edge of the sck clock (mosi needs
to be driven by the system on the falling edge of
the sck clock).
3. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
4. Data transmission:
- For write commands, the master continues
sending the 16-bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Maximum frequency for the SPI depends on the input
clock and type of sensor. The frequency is 1/6^th of the PLL
input clock or 1/30^th (in 10-bit mode) and 1/24^th (in 8-bit
mode) of the LVDS input clock frequency.
At nominal input frequency (62 Mhz / 310 MHz /
248 MHz), the maximum frequency for the SPI is 10 MHz.
Bursts of SPI commands can be issued by leaving at least
two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
ss_n
sck
mo si
SP I − W R ITE
t_sssck
ts ck
ts _mos i
th_mosi
A8
A7
..
..
..
A1
A0
`1'
D1 5
D14
..
..
..
..
D1
D0
t_sc ks s
miso
ss_n
sck
mo si
miso
t_sssck
ts_mosi
A8
A7
th_mosi
..
..
SPI − REA D
ts ck
..
A1
A0
`0'
ts _mi so
th_mi so
D1 5
D14
..
..
..
..
D1
D0
Figure 16. SPI Read and Write Timing Diagram
t_sc ks s
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