NOIV1SN1300A Datasheet, PDF (23/76 Pages) ON Semiconductor – VITA 1300 1.3 Megapixel 150 FPS Global Shutter CMOS Image Sensor

NOIV1SN1300A, NOIV2SN1300A
Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2
Upload #
Address
Data
2
32
0x2004
Disable logic clock
3
9
0x0009
Soft reset clock generator
V1-SN/SE 10-bit mode without PLL
1
34
0x0000
Disable logic blocks
2
32
0x2000
Disable logic clock
3
9
0x0009
Soft reset clock generator
V2-SN/SE 10-bit mode
1
34
0x0000
Disable logic blocks
2
32
0x200C
Disable logic clock
3
9
0x0009
Soft reset clock generator
Description
Disable Clock Management - Part 1
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
This action can be implemented with the SPI uploads as
shown in Table 14.
Table 14. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
1
16
0x0000
Disable PLL
2
8
0x0099
Soft reset PLL
3
20
0x0000
Configure clock management
Power Down Sequence
Figure 13 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
> 10us > 10us > 10us > 10us
Figure 13. Power Down Sequence
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