NOIS1SM1000S-HHC Datasheet, PDF (28/37 Pages) ON Semiconductor – STAR1000 1M Pixel Radiation Hard CMOS

NOIS1SM1000S, NOIS1SM1000A
Addressing Logic
The addressing logic allows direct addressing of rows and
columns. Instead of the one-hot shift registers that are often
used, address decoders are implemented. One can select a
line by presenting the required address to the address input
of the device and latching it to the Y- decoder logic.
Presenting the
X- address to the device address input and latching it to the
X- address decoder can select a column.
A typical line read out sequence first selects a line by
applying the Y-address to the Y-decoder. Activation of the
LD_Y input on the Y-logic connects the pixel outputs of the
selected line to the column amplifiers. The individual
column amplifier outputs are connected to the output
amplifier by applying the respective
X- addresses to the X- address decoder. Applying the
appropriate Y- address to the Y- decoder and activating the
“Reset” input reset a line. The integration time of a row is the
time between the last reset of this row and the time when it
is selected for read out.
The Y- decoder logic has two different reset inputs:
RESET and RESET_DS. Activation of RESET resets the
pixel to the Vdd level; activation of RESET_DS resets the
pixel to the voltage level on the VREF input. This feature
allows the application of the so called dual slope integration.
If dual slope integration is not needed, VREF is tied to Vdd
and RESET_DS must never be activated.
Column Amplifiers
All outputs from the pixels in a column are connected in
parallel to a column amplifier. This amplifier samples the
output voltage and the reset level of the pixel whose row is
selected at that moment and presents these voltage levels to
the output amplifier. As a result, the pixels are always reset
immediately after read out as part of the sample procedure.
Note that the maximum integration time of a pixel is the time
between two read cycles.
Output Amplifier and Analog Multiplexer
The output amplifier combines subtraction of pixel signal
level from reset level with a programmable gain amplifier.
Because the amplifier is AC coupled, it also contains a
provision to maintain and restore the proper DC level.
An analog signal multiplexing feeds the pixel signal to the
final unity gain buffer, providing the required drive
capability. Apart from the pixel signal, three other external
analog signals can be fed to the output buffer. All these
signals can be digitalised by the on-chip ADC if the output
of this buffer is externally connected to the input of the ADC.
The purpose of the additional analog inputs (A_IN1,
A_IN2, and A_IN3) is to allow the possibility of processing
other analog signals through the image sensors signal path.
These signals can then be converted by the ADC and
processed by the image controller FPGA. The additional
analog inputs are intended for low frequency or DC signals
and have a reduced bandwidth compared with the image
signal path.
ADC
The image sensor has a 10-bit ADC that is electrically
separated from the rest of the image sensor circuits and can
be powered down if an external ADC is used. The
conversion takes place at the falling edge of the clock and the
output pins can be disabled to allow operation of the device
in a bus structure.
Bayer Pattern
The STAR1000 is available in a color variant. Looking
from Top View, with Pin 1 left center, pixel red is (0,0) as
shown in Figure 6.
x_readout direction
Top View
STAR1000
Pixel Array
GB
(0,1) (1,1)
RG
(0,0) (1,0)
Figure 9. Bayer Pattern for STAR1000
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