NCP1060 Datasheet, PDF (25/30 Pages) ON Semiconductor – High-Voltage Switcher

NCP1060, NCP1063
Figure 48. Primary Inductance Current
Evolution in CCM
3. Lateral MOSFETs have a poorly doped
body−diode which naturally limits their ability to
sustain the avalanche. A traditional RCD clamping
network shall thus be installed to protect the
MOSFET. In some low power applications, a
simple capacitor can also be used since
Ǹ V_drain,max + V_in ) N @ ^ǒV_out ) V_f^Ǔ ) I_peak @
L_f
C_tot
(eq. 3)
where L_f is the leakage inductance, C_tot the total
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the N_P:N_S turn ratio, V_out the output
voltage, V_f the secondary diode forward drop and
finally, I_peak the maximum peak current. Worse case
occurs when the SMPS is very close to regulation,
e.g. the V_out target is almost reached and I_peak is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at V_in
= 375 Vdc). This voltage is given by the RCD clamp
installed from the drain to the bulk voltage. We will
see how to calculate it later on.
4. Calculate the maximum operating duty−cycle for
this flyback converter operated in CCM:
d_max
+
N
@
N @ ^ǒV_out @ V_f^Ǔ
ǒ_{Vout @ Vf}Ǔ _{) Vin,min}
+
1
+ 0.44
1
)
V_in,min
N@(V_out@V_f)
(eq. 4)
5. To obtain the primary inductance, we have the
choice between two equations:
L
+
ǒ_{Vin @ d}Ǔ²
f_sw @ K @ P_in
(eq. 5)
where
K
+
DI_L
I_Lavg
and defines the amount of ripple we want in CCM (see
Figure 48).
• Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
• Large K: approaching DCM where the RMS losses are
worse, but smaller inductance, leading to a better
leakage inductance.
From Equation 6, a K factor of 1 (50% ripple), gives an
inductance of:
L
+
(127
60k
@
@
0.44)²
1@5
+
10.04
mH
DI_L
+
V_in
L@
@d
f_sw
+
127 @ 0.44
10.04m @ 60k
+
92.8 mA peak to peak
The peak current can be evaluated to be:
I_peak
+
I_avg
d
)
DI_L
2
+
49.2 m
0.44
)
92.8
2
m
+
158
mA
On I_L, I_Lavg can also be calculated:
I_Lavg
+
I_peak
*
DI_L
2
+
158m
*
92.8m
2
+
111.6
mA
6. Based on the above numbers, we can now evaluate
the conduction losses:
Ǹ ǒ Ǔ I_d,rms +
d@
I_peak
2
*
I_peak
@
DI
L
)
DI_L
3
2
Ǹ ǒ Ǔ +
0.44 @
0.158²
*
0.158
@
0.0928
)
0.0928²
3
+ 57 mA
If we take the maximum R_DS(on) for a 125°C
junction temperature, i.e. 34 W, then conduction
losses worse case are:
P_cond + I_d,rms ² @ R_DS(on) + 110 mW
7. Off−time and on−time switching losses can be
estimated based on the following calculations:
ǒ Ǔ _{Poff + Ipeak @}
V_bulk ) V_clamp
2T_SW
@ t_off
(eq. 6)
+
0.158
@
(127 ) 100
2 @ 16.7 m
@
2)
@
10n
+ 15.5 mW
Where, assume the V_clamp is equal to 2 times of reflected
voltage.
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