NCP6121 Datasheet, PDF (22/28 Pages) ON Semiconductor – Dual Output 3 Phase +1/0 Phase Controller

NCP6121
R_CSN
+
L_PHASE
C_CSN * DCR
RCSN
CCSN
SWNx
DCR
LPHASE
1
2
VOUT
Figure 6.
The individual phase current is summed into to the PWM
comparator feedback in this way current is balanced is via
a current mode control approach.
Total Current Sense Amplifier
The NCP6121 uses a patented approach to sum the phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage
droop, total current limit, and the output current monitoring
functions. The total current signal is floating with respect to
CSREF. The current signal is the difference between
CSCOMP and CSREF. The Ref(n) resistors sum the signals
from the output side of the inductors to create a low
impedance virtual ground. The amplifier actively filters and
gains up the voltage applied across the inductors to recover
the voltage drop across the inductor series resistance (DCR).
Rth is placed near an inductor to sense the temperature of the
inductor. This allows the filter time constant and gain to be
a function of the Rth NTC resistor and compensate for the
change in the DCR with temperature.
Figure 7.
The DC gain equation for the current sensing:
ǒ Ǔ _{VCSCOMP−CSREF}
+
Rcs2
−
)
Rcs1*Rth
Rcs1)Rth
Rph
*
I_outTotal * DCR
(eq. 2)
Set the gain by adjusting the value of the Rph resistors.
The DC gain should set to the output voltage droop. If the
voltage from CSCOMP to CSREF is less than 100 mV at
ICCMAX then it is recommend to increase the gain of the
CSCOMP amp and add a resister divider to the Droop pin
filter. This is required to provide a good current signal to
offset voltage ratio for the ILIMIT pin. When no droop is
needed, the gain of the amplifier should be set to provide
~100 mV across the current limit programming resistor at
full load. The values of Rcs1 and Rcs2 are set based on the
100k NTC and the temperature effect of the inductor and
should not need to be changed. The NTC should be placed
near the closest inductor. The output voltage droop should
be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set
equal to the zero from the output inductor. This allows the
circuit to recover the inductor DCR voltage drop current
signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
of the time constant using commonly available values. It is
best to fine tune this filter during transient testing.
DCR@25° C
F_Z + _{2 * PI * LPHASE}
(eq. 3)
ǒ FP +
2 * PI *
1
(eq. 4)
Rcs1
)
Rcs1*Rth@25° C
Rcs1)Rth@25° C
*
(Ccs1
)
Ccs2)
Programming the Current Limit
The current limit thresholds are programmed with a
resistor between the ILIMIT and CSCOMP pins. The
ILIMIT pin mirrors the voltage at the CSREF pin and
mirrors the sink current internally to IOUT (reduced by the
IOUT Current Gain) and the current limit comparators. The
100% current limit trips if the ILIMIT sink current exceeds
10 mA for 50 ms. The 150% current limit trips with minimal
delay if the ILIMIT sink current exceeds 15 mA. Set the
value of the current limit resistor based on the
CSCOMP−CSREF voltage as shown below.
Rcs1*Rth
Rcs2
)
Rcs1)Rth
Rph
*
ǒ_IoutLIMIT
*
DCR^Ǔ
R_LIMIT +
10m
(eq. 5)
or
V_{CSCOMPudahsCSREF@ILIMIT}
R_LIMIT + LIMIT +
10m
(eq. 6)
Programming DROOP and DAC Feed−Forward Filter
The signals DROOP and CSREF are differentially
summed with the output voltage feedback to add precision
voltage droop to the output voltage. The total current
feedback should be filtered before it is applied to the
DROOP pin. This filter impedance provides DAC
feed−forward during dynamic VID changes. Programming
this filter can be made simpler if CSCOMP−CSREF is equal
to the droop voltage. Rdroop sets the gain of the DAC
feed−forward and Cdroop provides the time constant to
cancel the time constant of the system per the following
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