NCP6121 Datasheet, PDF (21/28 Pages) ON Semiconductor – Dual Output 3 Phase +1/0 Phase Controller

NCP6121
BOOT VOLTAGE PROGRAMMING
The NCP6121 has a Vboot voltage register that can be
externally programmed for each output. The VBOOTA also
provides a feature that allows the “+1” single phase output
to be disabled and effectively removed from the SVID bus.
If the single phase output is disabled it alters the SVID
address setting table to allow the multi−phase rail to show up
at an even or odd address. See the Boot Voltage Table below.
Table 3. BOOT VOLTAGE TABLE
Boot Voltage (V)
Resistor Value (W)
0
10k
0.9
25k
1.0
45k
1.1
70k
1.2
95k
1.35
125k
1.5
165k
VCC
Shutdown (VbootA only)
ADDRESSING PROGRAMMING
The NCP6121 supports seven possible dual SVID device
addresses and eight possible single device addresses. Pin 32
(PWM1/ADDR) is used to set the SVID address. On power
up a 10 mA current is sourced from this pin through a resistor
connected to this pin and the resulting voltage is measured.
The two tables below provide the resistor values for each
corresponding SVID address. For dual addressing follow
the Dual SVID Address Table. The address value is latched
at start−up. If VBOOTA is pulled to VCC the aux rail will
be removed from the SVID bus, the address will then follow
the Single Address SVID table below.
Table 4. DUAL SVID ADDRESS TABLE
Resistor
Value
Main Rail SVID Address
Aux Rail SVID
Address
10k
0000
0001
25k
0010
0011
45k
0100
0101
70k
0110
0111
95k
1000
1001
125k
1010
1011
165k
1100
1101
Table 5. SINGLE SVID ADDRESS TABLE
Resistor
Value
Main Rail SVID Address
(VBOOTA tied to VCC)
10k
0000
22k
0001
36k
0010
51k
0011
68k
0100
91k
0101
120k
0110
160k
0111
220k
1000
Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense the
output voltage of the regulator. The VSP and VSN inputs
should be connected to the regulator’s output voltage sense
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
V_DIFOUT + ^ǒV_VSP * V_VSN^Ǔ ) ^ǒ1.3 V * V_DAC^Ǔ
ǒ Ǔ _{) VDROOP * VCSREF}
(eq. 1)
High Performance Voltage Error Amplifier
A high performance error amplifier is provided for high
bandwidth transient performance. A standard Type 3
compensation circuit is normally used to compensate the
system.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense
that phase current for current balance. The inputs to the
CSNx and CSPx pins are high impedance inputs. It is
recommended that any external filter resistor RCSN not
exceed 10 kW to avoid offset issues with leakage current. It
is also recommended that the voltage sense element be no
less than 0.5 mW for accurate current balance. Fine tuning
of this time constant is generally not required.
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