NCP1651D Datasheet, PDF (21/32 Pages) ON Semiconductor – Single Stage Power Factor Controller

NCP1651
The input to the current sense amplifier is a common base
configuration. The voltage developed across the current
shunt is sensed at the Is+ input. The amplifier input is
designed for positive going voltages only; the power stage
should resemble the configuration of the application circuit
in Figure 38.
Caution should be exercised when designing a filter
between the shunt resistor and this input, due to the low
impedance of this amplifier. Any series resistance due to a
filter, will create an offset of:
VOS = 50 mA × Rexternal
which will add a positive offset to the current signal. The effect
of this is that the AC error amplifier will try to compensate for
the average output current which appears never to go to zero,
and cause additional zero crossing distortion.
The voltage across the current shunt resistor is converted
into a current (i₁), which drives a current mirror. The output
of the i₁ current mirror is a high frequency signal that is a
replica of the instantaneous current in the switch. The
conversion of the current sense signal to current i₁ is:
i1 = Vis_+∕3 k
The PWM output sends that information directly to the
PWM input where it is added to the AC error amp signal and
the ramp compensation signal.
The Leading Edge Blanking circuit (LEB) interrupts the
current signal to the PWM comparator for the first 200 ns of
the switching pulse. This blanks out any spike that might
occur at turn on, which could cause false triggering of the
PWM comparator.
The other output of the i₁ mirror provides a voltage signal
to a buffer amplifier. This signal is the result of i₁ dropped
across an internal 30 kΩ resistor, and filtered by a capacitor
at pin 6. This signal, when properly filtered, will be the 2x
line frequency fullwave rectified sinewave. The filter pole
on pin 6 should be far enough below the switching frequency
to remove most of the high frequency component, but high
enough above the line frequency so as not to cause
significant distortion to the input fullwave rectified
sinewave waveform.
For a 100 kHz switching frequency and a 60 Hz line
frequency, a 10 kHz pole will normally work well. The
capacitor at pin 6 can be calculated knowing the desired pole
frequency by the equation:
C6
=
2
π
1
f30k
Where:
C₆ = Pin 6 capacitance (nF)
f = pole frequency (kHz)
or, for a 10 kHz pole, C₆ would be 0.5 nF.
The gain of the low frequency current buffer is set by the
value of the resistor at pin 7. The value of R7 determines the
scale factor between the peak current and the average
current. The average current will be that of the primary
waveform only, since the secondary current will not conduct
across the shunt resistor.
PWM Logic
The PWM and logic circuits are comprised of a PWM
comparator, an RS flip--flop (latch) and an OR gate. The
latch is Set dominant which means that if both R and S are
high the S signal will dominate and Q will be high, which
will hold the power switch off.
The NCP1651 uses a voltage mode Pulse Width
Modulation scheme based on a fixed frequency oscillator.
The oscillator outputs a ramp waveform as well as a pulse
which is coincident with the falling edge of the ramp. The
pulse is fed into the PWM latch and OR gate that follows.
During the pulse, the latch is reset, and the output drive is in
its low state.
On the falling edge of the pulse, the output drive goes high
and the power switch begins conduction. The instantaneous
inductor current is summed with the AC error amplifier
voltage and the ramp compensation signal to create a
complex waveform that is compared to the 4.0 volt reference
signal on the inverting input to the PWM comparator. When
the signal at the non--inverting input to the PWM comparator
exceeds 4.0 volts, the output of the PWM comparator
changes to a high state which drives one of the Set inputs to
the latch and turns the power switch off until the next
oscillator cycle.
The OR gate that follows the PWM is used to inhibit the
drive signal to the power switch. In addition to the oscillator
pulse, this gate receives a signal from the shutdown OR gate,
which can inhibit operation due to an overtemperature
condition, shutdown signal, or insufficient V_CC.
Driver
The output driver can be used to directly drive a FET, for
low and medium power applications, or a larger driver for
high power applications.
It is a complementary MOS, totem pole design, and is
capable of sourcing and sinking over 1.5 amps, with typical
rise and fall times of 50 ns with a 1.0 nF load. The totem pole
output has been optimized to minimize cross conduction
current during high speed operation.
Additional internal circuitry has been added to keep the
Driver in its low state whenever the Undervoltage Lockout
is active. This characteristic eliminates the need for an
external gate pulldown resistor.
Shutdown Modes and Logic
Overtemperature A temperature sensor and reference is
provided to monitor the junction temperature of the chip.
The chip will operate to a nominal temperature of 160C at
which time the output of the temperature sensor will change
to a low state. This will set the output of the shutdown
NAND gate high, which in turn will set the output of the
PWM OR gate high, and force the driver into a low state.
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