NCP1602 Datasheet, PDF (21/32 Pages) ON Semiconductor – Enhanced, High-Efficiency Power Factor Controller

NCP1602
Detailed Operating Description
Introduction
NCP1602 is designed to optimize the efficiency of your
PFC stage throughout the load range. In addition, it
incorporates protection features for rugged operation. More
generally, NCP1602 is ideal in systems where
cost−effectiveness, reliability, low stand−by power and high
efficiency are key requirements:
• Valley Synchronized Frequency Fold−back:
NCP1602 is designed to drive PFC boost stages in
so−called Valley Synchronized Frequency Fold−back
(VSFF). In this mode, the circuit classically operates in
Critical conduction Mode (CrM) when V_ctrl exceeds a
programmable value. When the V_ctrl is below this
preset level, NCP1602 linearly reduces the frequency
down to about 33 kHz before reaching the SKIP
threshold voltage (SKIP Mode versions [B**] and
[D**]). VSFF maximizes the efficiency at both nominal
and light load. In particular, stand−by losses are
reduced to a minimum. Similarly to FCCrM
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• SKIP Mode (Versions [B**] and [D**]):
to further optimize the efficiency, the circuit skips
cycles at low load current when V_ctrl reaches the SKIP
threshold voltage. This is to avoid circuit operation
when the power transfer is particularly inefficient at the
cost of current distortion. This SKIP function is not
present on versions [A**] and [C**]).
• Low Start−up Current and large V_CC range ([**A] &
[**B] versions): The start−up consumption of the
circuit is minimized to allow the use of
high−impedance start−up resistors to pre−charge the
V_CC capacitor. Also, the minimum value of the UVLO
hysteresis is 6 V to avoid the need for large V_CC
capacitors and help shorten the start−up time without
the need for too dissipative start−up elements. The
[**C] & [**D] version is preferred in applications
where the circuit is fed by an external power source
(from an auxiliary power supply or from a downstream
converter). Its maximum start−up level (11.25 V) is set
low enough so that the circuit can be powered from a
12−V rail. After start−up, the high V_CC maximum rating
allows a large operating range from 9.5 V up to 30 V.
• Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): Since PFC stages exhibit low
loop bandwidth, abrupt changes in the load or input
voltage (e.g. at start−up) may cause excessive over or
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
♦ NCP1602 linearly decays the power delivery to zero
when the output voltage exceeds 105% of its desired
level (soft OVP). If this soft OVP is too smooth and
the output continues to rise, the circuit immediately
interrupts the power delivery when the output
voltage is 107% above its desired level.
♦ NCP1602, dramatically speeds−up the regulation
loop when the output voltage goes below 95.5% of
its regulation level. This function is enabled only
after the PFC stage has started−up to allow normal
soft−start operation to occur.
• Safety Protections: Permanently monitoring the input
and output voltages, the MOSFET current and the die
temperature to protect the system from possible
over−stress making the PFC stage extremely robust and
reliable. In addition to the OVP protection, the
following methods of protection are provided:
♦ Maximum Current Limit: The circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
♦ Under−Voltage Protection: This circuit turns off
when it detects that the output voltage is below 12%
of the voltage reference (typically). This feature
protects the PFC stage if the ac line is too low or if
there is a failure in the feedback network (e.g., bad
connection).
♦ Brown−Out Detection: The circuit detects low ac
line conditions and stops operation thus protecting
the PFC stage from excessive stress.
♦ Thermal Shutdown: An internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
• Output Stage Totem Pole: NCP1602 incorporates a
−0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
NCP1602 Operation Modes
As mentioned, NCP1602 PFC controller implements a
Valley Synchronized Frequency Fold−back (VSFF) where:
♦ The circuit operates in classical Critical conduction
Mode (CrM) when V_ctrl exceeds a programmable
value V_ctrl,th,*.
♦ When V_ctrl is below this V_ctrl,th,*, the NCP1602
linearly reduces the operating frequency down to
about 33 kHz
♦ When Vctrl reaches V_crtl minimum value or the V_ctrl
SKIP mode threshold, the system works in low
frequency burst mode.
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