NB100EP223 Datasheet, PDF (2/10 Pages) ON Semiconductor – 3.3V1:22 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Output Enable

NB100EP223
V_CC0
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
V_CC0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
NB100EP223
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
V_CC0
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
V_CC0
All V_CC, V_CCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (V_CC 0 V_CCO).
The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally.
Figure 1. 64−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
Table 2. FUNCTION TABLE
PIN
FUNCTION
OE* CLK_SEL
Q0−Q21
Q0−Q21
HSTL_CLK*, HSTL_CLK**
HSTL, LVPECL or LVDS Differential Inputs
L
LVPECL_CLK*, LVPECL_CLK** LVPECL Differential Inputs
L
CLK_SEL**
LVCMOS/LVTTL Input CLK Select
H
OE**
LVCMOS/LVTTL Output Enable
H
Q0−Q21, Q0−Q21
HSTL Differential Outputs
L
L
H
H
L
H
L
HSTL_CLK
HSTL_CLK
H
LVPECL_CLK LVPECL_CLK
V_CC
V_CCO
GND***
Positive Supply_Core (3.0 V − 3.6 V)
* The OE (Output Enable) signal is synchronized with the
Positive Supply_HSTL Outputs(1.6V−2.0V) _{rising edge of the HSTL_CLK and LVPECL_CLK signal.}
Ground
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally.
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