MC74HC125ADR2G Datasheet, PDF (2/8 Pages) ON Semiconductor – Quad 3-State Noninverting Buffers

MC74HC125A, MC74HC126A
PIN ASSIGNMENT
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 V_CC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
FUNCTION TABLE
HC125A
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
HC126A
Inputs Output
A OE Y
HH H
LH
L
XL
Z
LOGIC DIAGRAM
HC125A
Active−Low Output Enables
A1
2
3
Y1
HC126A
Active−High Output Enables
A1
2
3
Y1
OE1
1
5
A2
OE1
1
6
5
Y2
A2
6
Y2
OE2
4
9
A3
OE2
4
8 _Y3
A3
9
8
Y3
OE3
10
12
A4
13
OE4
OE3
10
11
12
Y4
A4
13
OE4
PIN 14 = V_CC
PIN 7 = GND
11
Y4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VCC DC Supply Voltage (Referenced to GND)}
– 0.5 to + 7.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin DC Input Voltage (Referenced to GND)}
– 0.5 to V_CC + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vout DC Output Voltage (Referenced to GND)}
– 0.5 to V_CC + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I_in
DC Input Current, per Pin
± 20
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Iout ^{DC Output Current, per Pin}
± 35
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^ICC ^{DC Supply Current, V}CC ^{and GND Pins}
± 75
mA
P_D Power Dissipation in Still Air
Plastic DIP†
750
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{SOIC Packageâ€} 
500
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TSSOP Package†
450
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T_stg Storage Temperature
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^TL ^{Lead Temperature, 1 mm from Case for 10 Seconds}
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Plastic DIP, SOIC or TSSOP Package)}
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Min
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ V_CC DC Supply Voltage (Referenced to GND)
2.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Vin^{, V}out ^{DC Input Voltage, Output Voltage}
0
(Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{TA Operating Temperature, All Package Types}
– 55
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tr, tf Input Rise and Fall Time}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
V_CC = 2.0 V
0
V_CC = 4.5 V
0
V_CC = 6.0 V
0
Max
6.0
V_CC
Unit
V
V
+ 125 _C
1000 ns
500
400
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V_in and
V_out should be constrained to the
range GND v (V_in or V_out) v V_CC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V_CC).
Unused outputs must be left open.
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