MC74HC125ADR2G Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad 3-State Noninverting Buffers

MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14
1
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HC12xAN
AWLYYWWG
14
SOIC−14
D SUFFIX
CASE 751A
1
HC12xAG
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
12xA
ALYWG
G
1
x
A
L, WL
Y, YY
W, WW
G or G
= 5, 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
May, 2013 − Rev. 14
Publication Order Number:
MC74HC125A/D